In a memory chip, the possibility arises that due to in-process problems or others a faulty part which is unable to perform a proper storage action, namely an error bit will be developed. If an error bit, even though a single one, exists in a memory chip, the memory chip will have to be discarded as a defective item, which gives rise to a problem of deterioration in manufacturing yields.
FIG. 17 is a block diagram showing the constitution of a memory chip 1 of conventional design. This is a typical prior art practice disclosed in Japanese Unexamined Patent Publication JP-A 11-250691 (1999). The memory chip 1 disclosed in JP-A 11-250691 includes, in addition to a main memory cell 4, a row-wise redundant memory cell 2 and a column-wise redundant memory cell 3 as an excess of the storage capacity necessary for the normal operation of the memory chip 1. If an error bit exists in the main memory cell 4, the error bit will be replaced with the corresponding one of the row-wise redundant memory cell 2 and the column-wise redundant memory cell 3 to make the memory chip 1 as a whole a conforming item.
The memory chip 1 is composed of: the main memory cell 4; the row-wise redundant memory cell 2; the column-wise redundant memory cell 3; a first demultiplexer 5; a first fuse circuit 6; a second demultiplexer 7; a second fuse circuit 8; a redundant row selector 9; a redundant column selector 10; a read/write control section 11; and a redundancy execution signal terminal 12. The main memory cell 4 for storing data stores data at the intersection of two straight lines intersecting at right angles, namely a data line and a word line. The first and second demultiplexers 5 and 7 are of circuits for allowing selection of the data line and the word line in the main memory cell 4. The row-wise redundant memory cell 2 and the column-wise redundant memory cell 3 each serve as a substitute for a defective memory cell in the event of for example a break in the data line as well as the word line of the main memory cell 4.
When some data line as well as word line of the main memory cell 4 is found to be faulty during an inspection/repair process in the course of the manufacture of the memory chip, a redundancy execution signal is impressed at the redundancy execution signal terminal 12. Whereupon, the line corresponding to the data line as well as the word line to be replaced is addressed, and the corresponding value determined in the redundant row selector 9 and the redundant column selector 10 is stored. Moreover, the output from the first and second demultiplexers 5 and 7 corresponding to the data line as well as the word line to be replaced is negated by the action of the first and second fuse circuits 6 and 8 to permit of adjustment so that upon the designation of the corresponding value, a target error bit of the main memory cell 4 is brought into an inactive state. In this way, the error bit of the main memory cell 4 can be replaced with the row-wise redundant memory cell 2 as well as the column-wise redundant memory cell 3 successfully, whereby making it possible to operate the main memory cell 4 as a conforming component.
In the memory chip 1, error bits arise in the main memory cell 4 statistically in a random fashion. Since the number of error bits per memory chip ranges with a statistical probability distribution, it follows that the storage capacity of the row-wise redundant memory cell 2 as well as the column-wise redundant memory cell 3 required to accomplish a redundancy-based relief is determined in view of a tradeoff between expected yield improvements which are achieved by dint of the redundancy-based relief and an increase of the size of the memory chip 1 entailed by the addition of the row-wise redundant memory cell 2 and the column-wise redundant memory cell 3. It will thus be seen that there arises a memory chip that failed to recover through the redundancy-based relief, namely a memory chip that has to be discarded as a defective item, with certain probability.